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Click on the image to get a bigger one !
The ABCD design is based upon the SCT128B prototype chip and the ABC design.
The core of the SCT128B chip, i.e. the analogue front-end, the binary pipeline
and the readout buffer is implemented in the ABCD design with some minor modifications.
It has been design at Cern by:
- Wladyslaw Dabrowski
- Jan Kaplon
- Robert Szczygiel
- Daniel La Marra
- Francis Anghinolfi
- Gerrit Meddeler
The major improvement, compared to the prototype SCT128B, is the "sparse" read out, i.e. only the data corrisponding to hit strips are read out. Click on the picture on the right to get the ABCD block diagram.
Test setup [ps] :
Test parameters:
- VDD=4.0 Volts VCC=3.5 Volts
- Input transistor current choosen on a chip by chip base in the range 193.2-211.6 muA
- Shaper current choosen on a chip by chip base in the range 19.2-22.8 muA
- Edge detection circuitry enable
- Edge data compression criteria (01X)
Measured quantities:
- Threshold scans (example at 4 fC [ps] )
- Error function fit to S_curves: 50% values and noise [ps]
- Linear fit between 2.0-4.0 fC [ps]
- Gain from linear fit [ps]
- Offset from linear fit [ps]
- ENC at 1fC extrapolated from the gain and the noise at 3.5fC [ps]
For modules results look at Module page
- Front end parameters settings:
- According to the specifications, the ABCD chips should work for a wide range of the front-end settings namely 100-300 muA for the input transistor
current and 10-30 muA for the shaper current. This was not the case
for the analysed batch. In fact the process specifications were not fully
met during the fabrication of this batch: the beta is lower than the
specified value and the resistors are at the high end of the specifications.
The result is that the chip can operate only in a very narrow range of the
bias settings. So, during the tests, the front end parameters working points
were determined chip by chip. The paramenters depends not only on the
chip itself but also on the number of chips placed on the hybrid
and on the set up.
A good set of parameters is the one that meets best the following
requirements:
stability of the front-end responce,
high gain (around 100 mV/fC), low noise (less than 900 ENC) and uniform
noise distribution along the channels.
- Low efficiency channels:
- Looking at the S-curve of some chips ( [ps] ),
it is easy to spot that some channels
never reach 100% efficiency even for low thresholds.
A more
detailed analysis of these channels show that for some of them it is possible to recuperate the lost events in the time slot following the triggered one,
while for some others that's not possibile. Most likely
the inefficiency of the second group of channels can have the following
explanation: in the pipeline the data from each channel is multiplexed into 12
subchannels, each 12 cell long. If one of this twelve subchannels
fails (e.g. it has one dead cell) then each 12th data for that
channel is lost. As a result we get 91.6% efficiency for that channel.
For two or three subchannels broken we will get 83.3% and 75% efficiency
respectively. This is compatible with the levels of inefficiency
observed for these channels.
- Trailer from the last chip:
- The ABCD internal logic requires that the logical level of
data_in-data_inB lines
has to be "0" during the trailer transfer. If these lines are left floating, like on the last chip on the hybrid chain, the requirement may not
be satisfied. In order to go around this problem the
data_in-data_inB
lines's logical level should be forced to be "0" (for example they could be tied
to VDD and DGND). This problem should not arise in the case of double-sided detector with two hybrids connected together and fully populated.
However the revised ABCD design will solve this problem.
Last updated: 15-sep-1998 by DM