/************************************************************************** * * Title: pixelConfigStructures.h * Version: 11th November 2002 * * Description: * ROD Master DSP Pixel module configuration structures * and constant definitions. * * Author: John Richardson; john.richardson@cern.ch * * - Adjusted to make compatible with the SCT module structure & * existing c code by adding members to the PixelModule structure. * Structure PixelFETrims expanded to a full array * (was a bit-field). 14.03.03 dpsf * - Added FEIndex into PixelFEConfig struct 16 Apr 03 * - Added in the (virtual) MCC strobe register, so that the * count register modifications done in the pixel serial stream * building functions do not interfere with placing the module * in data taking mode. 10 Feb 04 dpsf * - Added the calCoeff structure, a separate structure which the * MDSP transfers to the SDSPs during run-time (module loading & * SDSP start-up), so they have enough information to perform * the vcal to electrons conversion. 28 Jan 05 dpsf **************************************************************************/ #ifndef PIXEL_CONFIG_STRUCTURES_H /* multiple inclusion protection */ #define PIXEL_CONFIG_STRUCTURES_H #include "processor.h" /* Up to 28 pixel modules, with gaps in module structure set where the corresponding data links are not connected */ #define N_PIXEL_MODULES 28 #define N_PIXEL_EXTMODULES 0 /* no redundant command links */ #define N_PIXEL_TOTMODULES ((N_PIXEL_MODULES)+(N_PIXEL_EXTMODULES)) #define N_PIXEL_COLUMNS 18 #define N_PIXEL_ROWS 160 #define N_PIXEL_FE_CHIPS 16 #define N_I4_PIXEL_COLUMNS 80 #define N_I4_PIXEL_ROWS 336 #define N_I4_PIXEL_FE_CHIPS 2 #define FE_I1 1 #define FE_I2 2 #define FE_I4A 4 #define FE_I4B 5 #define FEI1 1 #define FEI2 2 #define FEI4A 4 #define FEI4B 5 #define MCC_I1 1 #define MCC_I2 2 #define NO_MCC 4 #define MCCI1 1 #define MCCI2 2 #define NOMCC 4 /* Default & off-ROD positions of a module's TTC fibres. The default primary TTC fibre location for a module is simply the module's position inside the structure set. */ #define DEFAULT_TTC 0x80 /* Default Link & Data Links which are turned off: */ #define DEFAULT_DATA_LINK 0x80 #define DATA_LINK_OFF 0xff #define PIXEL_STATIC_CONFIG 0 #define PIXEL_SCAN_CONFIG 1 /************* STRUCTURE DEFINITIONS ***********/ /* A small calibration coefficient structure containing just the vcal to electron conversion coefficients, for fitting on the SDSPs. */ typedef struct { FLOAT32 vcal[4]; FLOAT32 cap[2]; UINT8 capSel; UINT8 unused[3]; UINT32 unused1; } ChipCoeff; typedef struct { ChipCoeff fe[N_PIXEL_FE_CHIPS]; } CalCoeff; typedef struct { //FE Command register UINT32 address; /* 5 bits */ UINT32 command; /* 32 bits */ } PixelFECommand; typedef struct { //FE global register //This is valid for both FE-I1 & 2, since the FE-I1 is a sub-set. UINT32 latency : 8; UINT32 dacIVDD2 : 8; UINT32 dacIP2 : 8; UINT32 dacID : 8; UINT32 dacIP : 8; UINT32 dacITRIMTH : 8; UINT32 dacIF : 8; UINT32 dacITH1 : 8; UINT32 dacITH2 : 8; UINT32 dacIL : 8; UINT32 dacIL2 : 8; UINT32 dacITRIMIF : 8; UINT32 dacSpare : 8; UINT32 threshTOTMinimum : 8; UINT32 threshTOTDouble : 8; UINT32 hitbusScaler : 8; UINT32 capMeasure : 6; UINT32 gdac : 5; UINT32 selfWidth : 4; UINT32 selfLatency : 4; UINT32 muxTestPixel : 2; UINT32 spare : 2; UINT32 aregTrim : 2; UINT32 aregMeas : 2; UINT32 dregTrim : 2; UINT32 dregMeas : 2; UINT32 parity : 1; UINT32 dacMonLeakADC : 9; UINT32 dacVCAL : 10; /* extended to 10 bit for FE2/3 */ UINT32 widthSelfTrigger : 4; UINT32 muxDO : 4; /* note: dynamically defined */ UINT32 muxMonHit : 4; UINT32 muxEOC : 2; UINT32 frequencyCEU : 2; UINT32 modeTOTThresh : 2; UINT32 enableTimestamp : 1; UINT32 enableSelfTrigger : 1; UINT32 enableHitParity : 1; UINT32 monMonLeakADC : 1; UINT32 monADCRef : 1; UINT32 enableMonLeak : 1; UINT32 statusMonLeak : 1; UINT32 enableCapTest : 1; UINT32 enableBuffer : 1; UINT32 enableVcalMeasure : 1; UINT32 enableLeakMeasure : 1; UINT32 enableBufferBoost : 1; UINT32 enableCP8 : 1; UINT32 monIVDD2 : 1; UINT32 monID : 1; UINT32 enableCP7 : 1; UINT32 monIP2 : 1; UINT32 monIP : 1; UINT32 enableCP6 : 1; UINT32 monITRIMTH : 1; UINT32 monIF : 1; UINT32 enableCP5 : 1; UINT32 monITRIMIF : 1; UINT32 monVCAL : 1; UINT32 enableCP4 : 1; UINT32 enableCinjHigh : 1; UINT32 enableExternal : 1; UINT32 enableTestAnalogRef : 1; UINT32 enableDigital : 1; UINT32 enableCP3 : 1; UINT32 monITH1 : 1; UINT32 monITH2 : 1; UINT32 enableCP2 : 1; UINT32 monIL : 1; UINT32 monIL2 : 1; UINT32 enableCP1 : 1; UINT32 enableCP0 : 1; UINT32 enableHitbus : 1; UINT32 monSpare : 1; UINT32 enableAregMeas : 1; UINT32 enableAreg : 1; UINT32 enableLvdsRegMeas : 1; UINT32 enableDregMeas : 1; UINT32 enableTune : 1; UINT32 enableBiasComp : 1; UINT32 enableIpMonitor : 1; } PixelFEGlobal; typedef struct { //Pixel-level control bits UINT32 maskEnable[5][N_PIXEL_COLUMNS]; /* 32 bits, one bit per pixel thus 5 words per column */ UINT32 maskSelect[5][N_PIXEL_COLUMNS]; UINT32 maskPreamp[5][N_PIXEL_COLUMNS]; UINT32 maskHitbus[5][N_PIXEL_COLUMNS]; } PixelFEMasks; typedef struct { //Trim DACs: UINT8 dacThresholdTrim[N_PIXEL_ROWS][N_PIXEL_COLUMNS]; /*: 5; Currently 5 bits per pixel, will change in next iteration of FE */ UINT8 dacFeedbackTrim[N_PIXEL_ROWS][N_PIXEL_COLUMNS]; /*: 5; "" */ } PixelFETrims; typedef struct { /* Sub-structure for calibration of injection-capacitors, VCAL-DAC and leakage current measurement */ FLOAT32 cinjLo; FLOAT32 cinjHi; FLOAT32 cinjMed; FLOAT32 vcalCoeff[4]; FLOAT32 chargeCoeffClo; //dpsf: ? FLOAT32 chargeCoeffChi; FLOAT32 chargeOffsetClo; FLOAT32 chargeOffsetChi; FLOAT32 monleakCoeff; /* need MCC time calibration also //dpsf: ? */ } PixelFECalib; typedef struct { //MCC registers UINT16 regCSR; UINT16 regLV1; UINT16 regFEEN; UINT16 regWFE; UINT16 regWMCC; UINT16 regCNT; UINT16 regCAL; UINT16 regPEF; UINT16 regWBITD; UINT16 regWRECD; UINT16 regSBSR; /* Strobe duration is a virtual register (shared with CNT); when preparing the modules for data this value is substituted for the count. */ UINT16 regSTR; } PixelMCCRegisters; typedef struct { //FE level parameters UINT32 FEIndex; PixelFECommand FECommand; PixelFEGlobal FEGlobal; PixelFEMasks FEMasks; PixelFETrims FETrims; PixelFECalib FECalib; } PixelFEConfig; typedef struct { UINT8 tdac, prevTdac; UINT8 fdac, prevFdac; } PixelTrimScanData; typedef struct { //FE global register UINT32 TrigCnt; UINT32 Conf_AddrEnable; UINT32 CFGspare2; UINT32 ErrMask0; UINT32 ErrMask1; UINT32 PrmpVbpRight; UINT32 Vthin; UINT32 DisVbn_CPPM; UINT32 PrmpVbp; UINT32 TdacVbp; UINT32 DisVbnA; UINT32 Amp2Vbn; UINT32 Amp2VbpFol; UINT32 PrmpVbpTop; UINT32 Amp2Vbp; UINT32 FdacVbn; UINT32 Amp2Vbpf; UINT32 PrmpVbnFol; UINT32 PrmpVbpLeft; UINT32 PrmpVbpf; UINT32 PrmpVbnLcc; UINT32 spare; UINT32 PxStrobes; UINT32 PxS0; UINT32 PxS1; UINT32 LVDSDrvIref; UINT32 BonnDac; UINT32 PLLbias; UINT32 LVDSDrvVos; UINT32 TempSensBias; UINT32 PLLCPBias; UINT32 Reg17Spare; UINT32 PlsrIdacRamp; UINT32 Reg18Spare; UINT32 PlsrVgOPamp; UINT32 PlsrDacBias; UINT32 Reg19Spare; UINT32 vthin_AltCoarse; UINT32 vthin_AltFine; UINT32 PlsDAC; UINT32 DIGHITIN_Sel; UINT32 DINJ_Override; UINT32 HITLD_In; UINT32 Plsspare; UINT32 FENDSpare1; UINT32 Colpr_Addr; UINT32 Colpr_Mode; UINT32 FENDSpare2; UINT32 ColMask0; UINT32 ColMask1; UINT32 ColMask2; UINT32 TrigLat; UINT32 CMDcnt; UINT32 StopModeCnfg; UINT32 HitDisableCnfg; UINT32 CLKPLLCoreEnable; UINT32 FE_Clk_pulse; UINT32 Latch_en; UINT32 SR_clr; UINT32 CalEn; UINT32 CLKspare; UINT32 GateHitOr; UINT32 Rd_skipped; UINT32 Rd_Errors; UINT32 Stop_Clk; UINT32 Efuse_sense; UINT32 LVDSDrvSet06; UINT32 PLLSpare; UINT32 EN40M; UINT32 EN80M; UINT32 CLK0_S012; UINT32 CLK1_S012; UINT32 EN160M; UINT32 EN320M; UINT32 LVDSspare; UINT32 Disable8B10B; UINT32 Clk2OutCnfg; UINT32 EmptyRecord; UINT32 LVDSspare2; UINT32 LVDSDrvEn; UINT32 LVDSDrvSet30; UINT32 LVDSDrvSet12; UINT32 PlsrRiseUpTau; UINT32 PlsrPwr; UINT32 PlsrDelay; UINT32 PlsrExtDigCalSW; UINT32 PlsrExtAnaCalSW; UINT32 PlsrSpare; UINT32 Efusedc0; UINT32 Efusedc1; UINT32 Efusedc2; UINT32 Efusecref; UINT32 Efusevref; UINT32 Chip_SN; // new for FE-I4B UINT32 Reg1Spare; UINT32 SmallHitErase; UINT32 Eventlimit; UINT32 BufVgOpAmp; UINT32 Reg6Spare; UINT32 Reg9Spare; UINT32 GADCOpAmp; UINT32 VrefDigTune; UINT32 VrefAnTune; UINT32 Reg27Spare1; UINT32 GADC_Enable; UINT32 ShiftReadBack; UINT32 TmpSensDiodeSel; UINT32 TmpSensDisable; UINT32 IleakRange; UINT32 Reg30Spare; UINT32 GADCSel; UINT32 Reg34Spare1; UINT32 PrmpVbpMsnEn; UINT32 Reg34Spare2; } PixelFEI4Global; /* typedef struct { //Pixel-level control bits */ /* UINT32 maskEnable [N_I4_PIXEL_COLUMNS/2][N_I4_PIXEL_ROWS/16]; /\* 32 bits, one bit per pixel thus 21 words per DC *\/ */ /* UINT32 maskInjCapH[N_I4_PIXEL_COLUMNS/2][N_I4_PIXEL_ROWS/16]; */ /* UINT32 maskInjCapL[N_I4_PIXEL_COLUMNS/2][N_I4_PIXEL_ROWS/16]; */ /* UINT32 maskIleak [N_I4_PIXEL_COLUMNS/2][N_I4_PIXEL_ROWS/16]; */ /* } PixelFEI4Masks; */ typedef struct { //Trim DACs: UINT8 dacThresholdTrim[N_I4_PIXEL_COLUMNS][N_I4_PIXEL_ROWS]; /* 5 bits per pixel */ UINT8 dacFeedbackTrim [N_I4_PIXEL_COLUMNS][N_I4_PIXEL_ROWS]; /* 4 bits per pixel */ } PixelFEI4Trims; typedef struct { //FE level parameters UINT32 FEIndex; PixelFECommand FECommand; PixelFEI4Global FEGlobal; UINT8 FEMasks[N_I4_PIXEL_COLUMNS][N_I4_PIXEL_ROWS]; // all masks combined, i.e. 4 bits per pixel PixelFEI4Trims FETrims; PixelFECalib FECalib; } PixelFEI4Config; typedef struct { /* FE module-level options: */ UINT16 maskEnableFEConfig; /* 16 bits, one per FE */ UINT16 maskEnableFEScan; UINT16 maskEnableFEDacs; UINT8 feFlavour; UINT8 mccFlavour; /* FE configurations: */ PixelFEConfig FEConfig[N_PIXEL_FE_CHIPS+1]; PixelFEI4Config FEI4Config[N_I4_PIXEL_FE_CHIPS+1]; /* MCC configuration */ PixelMCCRegisters MCCRegisters; /* The current (uniform) value for the DACs of each pixel during a DAC scan */ PixelTrimScanData trimScanData; char idStr[256]; /* Module identification string */ UINT8 present; /* Module is physically present. Does not need setting externally; handled by the Master DSP. */ UINT8 active; /* 1 -> participates in scans */ /* 0 -> registers unchanged during scanning */ UINT8 moduleIdx; /* Copy of the module's index for access from a pointer */ UINT8 groupId; /* The ID of the module's group. This is used to indicate which slave DSP will receive the module's data (if group based distribution is set), and also to allow different module groups to be triggered independently (for cross-talk studies). valid range: [0,7] */ UINT8 pTTC; /* primary TX channel */ UINT8 rx; /* data link used by module */ UINT8 unused1[2]; UINT32 unused2[0x6b7]; /* align module structures on convenient boundary */ } PixelModule; /* declare N_PIXEL_CONFIG_SETS structure for each of N_PIXEL_MODULES */ #endif /* multiple inclusion protection */