#taskdefine task1 comm,wrRegister,vthin,24 comm,rdRegister,tdacvbp comm,rdRegister,vthin endtasksleep,100 task2 comm,rdRegister,tdacvbp comm,wrRegister,tdacvbp,100 comm,rdRegister,tdacvbp endtask mask_errors comm,wrRegister,errmask0,65535 comm,wrRegister,errmask1,65535 endtask select_all_double_columns comm,wrRegister,Colpr_Mode, 3 comm,wrRegister,Colpr_addr, 0 endtask select_double_column_0 comm,wrRegister,Colpr_Mode, 0 comm,wrRegister,Colpr_addr, 0 comm,setDCIdx,0 endtask select_normal_shift_mode comm,wrRegister,S0,0 comm,wrRegister,S1,0 comm,wrRegister,HITLD_IN,0 endtask select_copy_shift_mode comm,wrRegister,S0,1 comm,wrRegister,S1,1 comm,wrRegister,HITLD_IN,0 endtask set_CalEn comm,wrRegister,GR27,32784 endtask set_SrClr comm,wrRegister,GR27,32776 endtask set_LatchEn comm,wrRegister,GR27,32772 endtask set_FeClkPulse comm,wrRegister,GR27,32770 endtask set_ErrorRequ comm,wrRegister,GR27,36864 endtask set_all_pixel_strobes comm,wrRegister,PxStr_FDAC,15 comm,wrRegister,PxStr_Imon,1 comm,wrRegister,PxStr_CinjS,1 comm,wrRegister,PxStr_CinjL,1 comm,wrRegister,PxStr_TDAC,31 comm,wrRegister,PxStr_OE,1 endtask deselect_all_pixel_strobes comm,wrRegister,PxStr_FDAC,0 comm,wrRegister,PxStr_Imon,0 comm,wrRegister,PxStr_CinjS,0 comm,wrRegister,PxStr_CinjL,0 comm,wrRegister,PxStr_TDAC,0 comm,wrRegister,PxStr_OE,0 endtask set_pixel_enable comm,wrRegister,PxStr_OE,1 endtask set_all_pixel_shift_register_bits comm,wrRegister,S0,1 comm,wrRegister,S1,0 comm,wrRegister,HITLD_IN,0 task,set_FeClkPulse comm,glbpulse,4 task,select_normal_shift_mode endtask set_pixel_shift_register_bit0 task,select_normal_shift_mode comm,wrFE,000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 endtask clear_pixel_shift_register task,select_normal_shift_mode task,set_SrClr comm,glbpulse,4 endtask clear_all_latches task,clear_pixel_shift_register task,set_LatchEn task,set_all_pixel_strobes comm,glbpulse,4 task,deselect_all_pixel_strobes endtask copy_inverse_pixel_latches_enable_bit task,select_copy_shift_mode comm,wrRegister,PxStr_OE,1 task,set_FeClkPulse comm,glbpulse,4 task,select_normal_shift_mode endtask inject_charge_and_goto_next_pixel comm,runmode comm,CAL comm,sendzeros,6 comm,LV1 comm,rdData comm,confmode task,set_FeClkPulse comm,glbpulse,2 comm,RowCnt++ endtask inject_charge_and_goto_next_pixel_1 comm,runmode comm,CAL comm,LV1 comm,rdData comm,confmode task,set_FeClkPulse comm,glbpulse,2 comm,RowCnt++ endtask inject_charge_and_goto_next_pixel_glbpls task,set_CalEn comm,glbpulse,10 comm,runmode comm,LV1 comm,rdData comm,confmode task,set_FeClkPulse comm,glbpulse,2 comm,RowCnt++ endtask wr_dob_loopback_refclk comm,wrRegister,PllIbias,15 comm,wrRegister,PllIcp,16 comm,wrRegister,PllEn,1 comm,wrRegister,EN_320M,0 comm,wrRegister,EN_160M,0 comm,wrRegister,EN_80M,0 comm,wrRegister,EN_40M,0 comm,wrRegister,CLK0_S2,0 comm,wrRegister,CLK0_S1,0 comm,wrRegister,CLK0_S0,0 comm,wrRegister,clk2OutCnfg,1 endtask wr_dob_loopback_320M comm,wrRegister,PllIbias,15 comm,wrRegister,PllIcp,16 comm,wrRegister,PllEn,1 comm,wrRegister,EN_320M,1 comm,wrRegister,EN_160M,0 comm,wrRegister,EN_80M,0 comm,wrRegister,EN_40M,0 comm,wrRegister,CLK0_S2,0 comm,wrRegister,CLK0_S1,0 comm,wrRegister,CLK0_S0,1 comm,wrRegister,clk2OutCnfg,1 endtask wr_dob_loopback_160M comm,wrRegister,PllIbias,15 comm,wrRegister,PllIcp,16 comm,wrRegister,PllEn,1 comm,wrRegister,EN_320M,0 comm,wrRegister,EN_160M,1 comm,wrRegister,EN_80M,0 comm,wrRegister,EN_40M,0 comm,wrRegister,CLK0_S2,1 comm,wrRegister,CLK0_S1,0 comm,wrRegister,CLK0_S0,0 comm,wrRegister,clk2OutCnfg,1 endtask wr_dob_loopback_80M comm,wrRegister,PllIbias,15 comm,wrRegister,PllIcp,16 comm,wrRegister,PllEn,1 comm,wrRegister,EN_320M,0 comm,wrRegister,EN_160M,0 comm,wrRegister,EN_80M,1 comm,wrRegister,EN_40M,0 comm,wrRegister,CLK0_S2,1 comm,wrRegister,CLK0_S1,0 comm,wrRegister,CLK0_S0,1 comm,wrRegister,clk2OutCnfg,1 endtask wr_dob_loopback_160M comm,wrRegister,PllIbias,15 comm,wrRegister,PllIcp,16 comm,wrRegister,PllEn,1 comm,wrRegister,EN_320M,0 comm,wrRegister,EN_160M,0 comm,wrRegister,EN_80M,0 comm,wrRegister,EN_40M,1 comm,wrRegister,CLK0_S2,1 comm,wrRegister,CLK0_S1,1 comm,wrRegister,CLK0_S0,0 comm,wrRegister,clk2OutCnfg,1 endtask test_rw_gr comm,wrrdRegister,i,0 comm,wrrdRegister,i,65535 comm,wrrdRegister,i,random comm,GRIdx++ endtask test_rw_gr_long comm,wrrdRegister,i,0 comm,wrrdRegister,i,65535 comm,wrrdRegister,i,0 comm,wrrdRegister,i,65535 comm,wrrdRegister,i,random comm,wrrdRegister,i,random comm,GRIdx++ endtask test_rw_shiftregister comm,wrrdShiftRegister,i,0 comm,wrrdShiftRegister,i,1 comm,wrrdShiftRegister,i,random comm,SRIdx++ endtask test_rw_shiftregister_debug comm,wrrdShiftRegister,i,0 comm,wrrdShiftRegister,i,1 comm,SRIdx++ endtask enable_pixel task,select_normal_shift_mode task,set_pixel_enable task,set_all_pixel_shift_register_bits task,set_LatchEn comm,glbpulse,4,//enable all pixels task,deselect_all_pixel_strobes task,clear_pixel_shift_register comm,wrRegister,PxStr_Imon,0 task,set_LatchEn comm,glbpulse,4 task,deselect_all_pixel_strobes comm,wrFE,1 endtask clear_chip comm,wrRegister,Colpr_Mode,0 comm,wrRegister,PxStr_FDAC,15 comm,wrRegister,PxStr_Imon,1 comm,wrRegister,PxStr_CinjS,1 comm,wrRegister,PxStr_CinjL,1 comm,wrRegister,PxStr_TDAC,31 comm,wrRegister,PxStr_OE,1 comm,wrRegister,Colpr_addr,0 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,1 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,2 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,3 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,4 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,5 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,6 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,7 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,8 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,9 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,10 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,11 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,12 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,13 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,14 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,15 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,16 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,17 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,18 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,19 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,20 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,21 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,22 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,23 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,24 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,25 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,26 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,27 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,28 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,29 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,30 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,31 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,32 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,33 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,34 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,35 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,36 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,37 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,38 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,Colpr_addr,39 comm,wrRegister,SrClr,1 comm,glbpulse,5 comm,wrRegister,SrClr,0 comm,wrRegister,LatchEn,1 comm,glbpulse,5 comm,wrRegister,LatchEn,0 comm,wrRegister,PxStr_FDAC,0 comm,wrRegister,PxStr_Imon,0 comm,wrRegister,PxStr_CinjS,0 comm,wrRegister,PxStr_CinjL,0 comm,wrRegister,PxStr_TDAC,0 comm,wrRegister,PxStr_OE,0 comm,wrRegister,Colpr_addr,0 endtask send_error_request comm,confmode comm,clearSRAM comm,sleep,10 task,set_ErrorRequ comm,glbpulse,5,//send read errors request comm,sleep,10 comm,dumpErrors endtask strobe_inject comm,sleep,5000 comm,StartInj endtask cal_pulse comm,CAL comm,sleep,5 endtask inc_trig comm,LV1 comm,rdData comm,glbpulse,2 endtask