unit ucamac;
interface
{camac make standard camac transfert see caution in subroutine description
 use online (or testonline ) before first transaction
 to be sure that the crate is online}
{Produit Nicolas 19.11.86}
{La Marra Daniel 28.11.91 modified for PC AT-386
                          because the 'portw' instruction are not same!}
{Produit Nicolas 95 corrected inhibit treatment}
{ ***********************************************************
  Marco Baioletti 19.9.96 completely modified 
  for PC PENTIUM and CAEN C-111
  ***********************************************************}

uses crt;

PROCEDURE testonline;
{display a message until crate power ok and online switch of controller in
 online position}
procedure camac(n,a,f:integer;var data:word);
{dont test validity of f and a and n}
{dont wait for done but that is always ok in that sort of single word transfer}
PROCEDURE camac2(n,a,f:INTEGER;VAR data:longint);
{300 microsec}
{dont test validity of f and a and n}
{dont wait for done but that is always ok in that sort of single word transfer}
FUNCTION qcamac:BOOLEAN;
{return q response of last transfert}
FUNCTION xcamac:BOOLEAN;
{return x response of last transfert}
FUNCTION lam:BOOLEAN; 
{return or of all lam in crate}
FUNCTION online:BOOLEAN;
{return online and power on status}
FUNCTION inhibit:BOOLEAN;
{return inhibit status}
PROCEDURE setinhibit;
PROCEDURE clearinhibit;
PROCEDURE zcamac;
{perform a z cycle}
PROCEDURE ccamac;
{perform a c cycle}
FUNCTION  rlam:longint;
{give out lam pattern}
FUNCTION  lamonstation(n:integer):BOOLEAN;
{test if station n assert lam}

implementation
CONST
      segm=$D000;
      rd0=0; rd1=1; rd2=2; rd3=3;
      wr0=0; wr1=1; wr2=2; wr3=3; wr4=4; wr5=5;
      status=rd3; station=wr4; subaddr=wr3; func=wr5;

FUNCTION donecamac:BOOLEAN;
(* MB *)
{return done bit = not busy}
BEGIN
 (* donecamac:=(port[ccontrolstatus] AND $80)<>0; *)
 donecamac:=true;
END; 

FUNCTION qcamac:BOOLEAN;
(* MB *)
BEGIN
 qcamac:=(mem[segm:status] AND $1)<>0;
END;

FUNCTION xcamac:BOOLEAN;
(* MB *)
BEGIN
 xcamac:=(mem[segm:status] AND $80)<>0;
END;

FUNCTION lam:BOOLEAN;
(* MB: DA IMPLEMENTARE *)
BEGIN
 lam:=rlam<>0
END; 

FUNCTION online:BOOLEAN;
(* MB: dummy *)
BEGIN
 online:=true
END;  

FUNCTION inhibit:BOOLEAN;
(* MB *)
BEGIN
 inhibit:=(mem[segm:status] AND 2)<>0;
END;

PROCEDURE setinhibit;
BEGIN
 mem[segm:func]:=33
END;

PROCEDURE clearinhibit;
BEGIN
 mem[segm:func]:=32
END;


PROCEDURE zcamac;
(* MB: dummy *)
BEGIN
 mem[segm:func]:=34
END;

PROCEDURE ccamac;
(* MB: dummy *)
BEGIN
 mem[segm:func]:=36
END;

function rlam:longint;
var lam:longint;
BEGIN
 mem[segm:func]:=56;
 lam:=mem[segm:rd2];
 lam:=(lam shl 8) + mem[segm:rd1];
 lam:=(lam shl 8) + mem[segm:rd0];
 rlam:=lam;
END;

FUNCTION lamonstation(n:integer):BOOLEAN;
BEGIN
  lamonstation:=(rlam AND (1 shl (n-1)))<>0;
END;

PROCEDURE testonline;
BEGIN
(* WHILE NOT online DO BEGIN
  WRITELN('PLEASE SWITCH CAMAC CRATE ON AND CAMAC CONTROLER ONLINE');
  DELAY(1000);
  if keypressed then halt;
 END; *)
END;

PROCEDURE camac2(n,a,f:INTEGER;VAR data:longint);
(* MB *)
VAR
   readf,writef:BOOLEAN;
BEGIN
 readf:=f<8;
 writef:=(f>15) AND (f<24);
 IF writef THEN BEGIN
  mem[segm:wr0]:=data AND $FF;
  mem[segm:wr1]:=(data shr 8) AND $FF;
  mem[segm:wr2]:=(data shr 16) AND $FF;
 END;
 mem[segm:station]:=n-1;
 mem[segm:subaddr]:=a;
 mem[segm:func]:=f;
 IF readf THEN BEGIN
   data:=port[$61];
   data:=mem[segm:rd2];
   data:=(data shl 8) or mem[segm:rd1];
   data:=(data shl 8) or mem[segm:rd0];
 END;
{IF NOT XCAMAC THEN WRITELN('CAMAC ERROR WITH N,A,F,D ',N:4,A:4,F:4,DATA:4);}
END;

PROCEDURE camac(n,a,f:INTEGER;VAR data:word);
(* MB *)
{CAUTION :: dont test validity of f and a and n}
VAR
   readf,writef:BOOLEAN;
BEGIN
 readf:=f<8;
 writef:=(f>15) AND (f<24);
 IF writef THEN BEGIN
  mem[segm:wr0]:=data and $FF;
  mem[segm:wr1]:=(data shr 8) and $ff;
 END;
 mem[segm:station]:=n-1;
 mem[segm:subaddr]:=a;
 mem[segm:func]:=f;
 IF readf THEN BEGIN
  delay(1);
  data:=mem[segm:rd1];
  data:=(data shl 8) or mem[segm:rd0];
 END;
{IF NOT XCAMAC THEN WRITELN('CAMAC ERROR WITH N,A,F,D ',N:4,A:4,F:4,DATA:4);}
END;

begin
 clearinhibit;
 mem[segm:func]:=40;
 mem[segm:wr0]:=$ff;
 mem[segm:wr1]:=$ff;
 mem[segm:wr2]:=$ff;
 mem[segm:func]:=42;
end.