#include <stdio.h>
#include <conio.h>
#include <time.h>
#include <dos.h>

#define Uses_TDR
#include "utils.h"

TTdrControl::TTdrControl() : TEppPort()
{
   dataCSR0 = csr0Default;
   VAnumber = defVAnumber;
   loadStatusRequest = TRUE;
   loadEventRequest  = TRUE;
   loadCheckEvent    = TRUE;
}

TTdrControl::~TTdrControl() {
}

void TTdrControl::initTDR() {
   setCSR0();
}

void TTdrControl::setCSR0() {
   writeData(portCSR0, dataCSR0);
}

void TTdrControl::setCSR0(ushort csr0) {
   dataCSR0 = csr0;
   setCSR0();
}

ushort TTdrControl::getCSR0() {
   return readDataWord(portCSR0);
}

uchar TTdrControl::getCSR1() {
   return readDataByte(portCSR1);
}

ulong TTdrControl::getCSR2() {
   ulong temp = readDataWord(portCSR2H);
   temp <<= 16;
   temp |= readDataWord(portCSR2L);
   return temp;
}

void TTdrControl::EppAddress(ushort addr) {
   writeData(portEppAddress, addr);
}

ushort TTdrControl::EppAddress() {
   return readDataWord(portEppAddress);
}

void TTdrControl::SlinkAddress(ushort addr) {
   writeData(portSlinkAddress, addr);
}

ushort TTdrControl::SlinkAddress() {
   return readDataWord(portSlinkAddress);
}

ushort TTdrControl::BootLength() {
   return readDataWord(portBootLength);
}

void TTdrControl::command(uchar cmd) {
   writeAddress(cmd);
}

int TTdrControl::bootXilinx(uchar tdr,uchar *data,ushort nbytes,ushort addr) {
   dataCSR0 |= csr0BootXilinx;
   setCSR0(dataCSR0);

   writeData(portEppAddress, addr);
   writeData(portRamRegister, data, (int) nbytes);
   writeData(portBootLength, (ushort) (nbytes + 1));
   writeData(portSlinkAddress, addr);

   switch ( tdr ) {
      case TDRS_A: writeAddress((uchar) cmdBootTDRS_A);break;
      case TDRS_B: writeAddress((uchar) cmdBootTDRS_B);break;
      case TDRK_A: writeAddress((uchar) cmdBootTDRK_A);break;
      case TDRK_B: writeAddress((uchar) cmdBootTDRK_B);break;
      case TDRS:   writeAddress((uchar) cmdBootTDRS);break;
      case TDRK:   writeAddress((uchar) cmdBootTDRK);break;
      case TDR_ALL:
      default:
         writeAddress((uchar) cmdBootTDRS);
	 writeAddress((uchar) cmdBootTDRK);
   }

   // Wait with timeout
   clock_t end_time = clock() + 18;
   while ( (getCSR1() & 8) ) {
      if ( clock() > end_time ) return FALSE;
   }

   dataCSR0 &= csr0BootDSP;
   setCSR0(dataCSR0);
   return TRUE;
}

int TTdrControl::bootDsp(uchar tdr,uchar *data,ushort nbytes,ushort addr) {
   writeData(portEppAddress, addr);
   writeData(portRamRegister, (ushort) 0xA5A5);
   writeData(portRamRegister, data, (int) nbytes);
   writeData(portBootLength, (ushort) (nbytes + 2));
   writeData(portSlinkAddress, addr);

   dataCSR0 &= csr0BootDSP;
   setCSR0(dataCSR0);
   dataCSR0 &= 0xF807;

   switch ( tdr ) {
      case TDRS_A:
         writeAddress((uchar) cmdBootTDRS_A);
         dataCSR0 |= (csr0EnLv1TdrsA | csr0EnReadyTdrsA);
         break;
      case TDRS_B:
         writeAddress((uchar) cmdBootTDRS_B);
         dataCSR0 |= (csr0EnLv1TdrsB | csr0EnReadyTdrsB);
	 break;
      case TDRK_A:
         writeAddress((uchar) cmdBootTDRK_A);
	 dataCSR0 |= (csr0EnLv1TdrkA | csr0EnReadyTdrkA);
         break;
      case TDRK_B:
         writeAddress((uchar) cmdBootTDRK_B);
         dataCSR0 |= (csr0EnLv1TdrkB | csr0EnReadyTdrkB);
         break;
      case TDRS:
         writeAddress((uchar) cmdBootTDRS);
	 dataCSR0 |= (csr0EnLv1TdrsA | csr0EnReadyTdrsA);
         dataCSR0 |= (csr0EnLv1TdrsB | csr0EnReadyTdrsB);
         break;
      case TDRK:
	 writeAddress((uchar) cmdBootTDRK);
         dataCSR0 |= (csr0EnLv1TdrkA | csr0EnReadyTdrkA);
         dataCSR0 |= (csr0EnLv1TdrkB | csr0EnReadyTdrkB);
         break;
      case TDR_ALL:
      default:
         writeAddress((uchar) cmdBootTDRS);
	 writeAddress((uchar) cmdBootTDRK);
         dataCSR0 |= (csr0EnLv1TdrsA | csr0EnReadyTdrsA);
         dataCSR0 |= (csr0EnLv1TdrsB | csr0EnReadyTdrsB);
         dataCSR0 |= (csr0EnLv1TdrkA | csr0EnReadyTdrkA);
         dataCSR0 |= (csr0EnLv1TdrkB | csr0EnReadyTdrkB);
   }

   // Wait with timeout
   clock_t end_time = clock() + 36;
   while ( (getCSR1() & 8) ) {
      if ( clock() > end_time ) return FALSE;
   }

   VAnumber = defVAnumber;
   setCSR0((dataCSR0 & 0x1FFF) | csr0VAnumber[VAnumber]);
   return TRUE;
}

void TTdrControl::resetBoard() {
   writeAddress((uchar) cmdResetBoard);
}

void TTdrControl::sendTrigger() {
   writeAddress((uchar) cmdSendTrigger);
}

// Attention reg=1 est partager avec RequestStatus, c'est pour ceci qu'
// il est important de noter 'loadRequestStatus' == FALSE

#define LgPED 4

ulong TTdrControl::sendPED(uchar tdr,ushort *data) {
   int reg=1,boucle;
   ushort *ptdata=data;

   getCSR1();
   loadStatusRequest=TRUE;
   ulong msg =msgSendPED;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) LgPED/2;
   writeData(portMessageLow[reg], temp);

   uchar cmd = regMessage[reg];

   cmd |= (cmdSelectStatus | tdr);
   writeAddress(cmd);

   cmd = regMessage[reg];

   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);
   delay(2);

   for (boucle=0;boucle<LgPED/2;boucle++) {
      writeData(portMessageHigh[reg], *ptdata++);
      writeData(portMessageLow[reg], *ptdata++);
      writeAddress(cmd);
      delay(2);
   };

  clock_t end_time = clock() + 6;
      while ( !(getCSR1() & 2) ) {
	 if ( clock() > end_time ) return 0L;
      }

   ulong temp2 = readDataWord(portCSR2H);
   temp2 <<= 16;
   temp2 += readDataWord(portCSR2L);
   return temp2;

};

#define LgSIGMA 4

ulong TTdrControl::sendSIGMA(uchar tdr,ushort *data) {
   int reg=1,boucle;
   ushort *ptdata=data;

   getCSR1();
   loadStatusRequest=TRUE;
   ulong msg =msgSendSIGMA;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) LgSIGMA/2;
   writeData(portMessageLow[reg], temp);

   uchar cmd = regMessage[reg];

   cmd |= (cmdSelectStatus | tdr);
   writeAddress(cmd);

   cmd = regMessage[reg];

   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);
   delay(2);

   for (boucle=0;boucle<LgSIGMA/2;boucle++) {
      writeData(portMessageHigh[reg], *ptdata++);
      writeData(portMessageLow[reg], *ptdata++);
      writeAddress(cmd);
      delay(2);
   };

  clock_t end_time = clock() + 6;
      while ( !(getCSR1() & 2) ) {
	 if ( clock() > end_time ) return 0L;
      }

   ulong temp2 = readDataWord(portCSR2H);
   temp2 <<= 16;
   temp2 += readDataWord(portCSR2L);
   return temp2;

};

#define LgTAB 2

ulong TTdrControl::sendTAB(uchar tdr,ushort *data) {
   int reg=1,boucle;
   ushort *ptdata=data;

   getCSR1();
   loadStatusRequest=TRUE;
   ulong msg =msgSendTAB;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) LgTAB/4;
   writeData(portMessageLow[reg], temp);

   uchar cmd = regMessage[reg];

   cmd |= (cmdSelectStatus | tdr);
   writeAddress(cmd);

   cmd = regMessage[reg];

   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);
   delay(2);

   for (boucle=0;boucle<LgTAB/2;boucle++) {
      writeData(portMessageHigh[reg], *ptdata++);
      writeData(portMessageLow[reg], *ptdata++);
      writeAddress(cmd);
      delay(2);
   };

  clock_t end_time = clock() + 6;
      while ( !(getCSR1() & 2) ) {
	 if ( clock() > end_time ) return 0L;
      }

   ulong temp2 = readDataWord(portCSR2H);
   temp2 <<= 16;
   temp2 += readDataWord(portCSR2L);
   return temp2;

};

void TTdrControl::getPED(uchar tdr) {
   int reg=1,boucle;

   loadStatusRequest=TRUE;
   ulong msg ; //= msgGetPED;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) 0;
   writeData(portMessageLow[reg], temp);

   writeAddress((uchar) (cmdSelectStatus | tdr));
   uchar cmd = regMessage[reg];

   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);

};

#define LgEvent 1540

ulong TTdrControl::sendEvent(uchar tdr,ushort *data) {
   int reg=1,boucle;
   ushort *ptdata=data;

   getCSR1();
   loadStatusRequest=TRUE;
   ulong msg =msgSendEvent;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) LgEvent/2;
   writeData(portMessageLow[reg], temp);

   uchar cmd = regMessage[reg];

   cmd |= (cmdSelectStatus | tdr);
   writeAddress(cmd);

   cmd = regMessage[reg];

   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);
   delay(2);

   for (boucle=0;boucle<LgEvent/2;boucle++) {
      writeData(portMessageHigh[reg], *ptdata);
      writeData(portMessageLow[reg], *ptdata);
      writeAddress(cmd);
      delay(2);
   };

  clock_t end_time = clock() + 6;
      while ( !(getCSR1() & 2) ) {
	 if ( clock() > end_time ) return 0L;
      }

   ulong temp2 = readDataWord(portCSR2H);
   temp2 <<= 16;
   temp2 += readDataWord(portCSR2L);
   return temp2;

};


int TTdrControl::getStatus(uchar tdr,ushort *ptdata) {
//   getCSR1();
   writeData(portSlinkAddress, (ushort) 0);
   writeData(portEppAddress, (ushort) 0);

   requestStatus(tdr);

   // Wait with timeout
   clock_t end_time = clock() + 6;
   while ( !(getCSR1() & 2) ) {
      if ( clock() > end_time ) return FALSE;
   }

   for(int boucle=0;boucle<16;boucle++) {
      *ptdata++=swapByte(readDataWord(portRamRegister));
   };

   return TRUE;
}

ushort TTdrControl::getEvent(uchar tdr, uchar *r) {
//   getCSR1();
   writeData(portSlinkAddress, (ushort) 0);
   writeData(portEppAddress, (ushort) 0);

   requestEvent(tdr);

   // Wait with timeout
   clock_t end_time = clock() + 6;
   while ( !(getCSR1() & 2) ) {
      if ( clock() > end_time ) return 0;
   }

   ushort *words = (ushort *) r;
   words[0] = readDataWord(portRamRegister);
   ushort len = swapByte(words[0]) * 2;
   readData(portRamRegister, &r[2], len);

   return (len + 2);
}

void TTdrControl::sendMessage(uchar tdr, ulong msg) {
   int reg = 3;
   ushort temp = (ushort) (msg >> 16);
   writeData(portMessageHigh[reg], temp);
   temp = (ushort) (msg & 0xFFFF);
   writeData(portMessageLow[reg], temp);
   uchar cmd = regMessage[reg];
   cmd |= (tdr == TDR_ALL ? cmdBrdCastMessage : (cmdSingleMessage | tdr));
   writeAddress(cmd);
}

ulong TTdrControl::checkMessage(int reg) {
   ulong temp = readDataWord(portMessageHigh[reg]);
   temp <<= 16;
   temp |= readDataWord(portMessageLow[reg]);
   return temp;
}

void TTdrControl::requestEvent(uchar tdr) {
   int reg = 0;

   writeAddress((uchar) (cmdSelectEvent | tdr));

   if ( loadEventRequest ) {
      ulong msg = msgRequestEvent;
      ushort temp = (ushort) (msg >> 16);
      writeData(portMessageHigh[reg], temp);
      temp = (ushort) (msg & 0xFFFF);
      writeData(portMessageLow[reg], temp);
      loadEventRequest = FALSE;
   }
   uchar cmd = regMessage[reg];
   cmd |= (tdr == TDR_ALL ? cmdBrdCastMessage : (cmdSingleMessage | tdr));
   writeAddress(cmd);
}

void TTdrControl::requestStatus(uchar tdr) {
   int reg = 1;

   if ( loadStatusRequest ) {
      ulong msg = msgRequestStatus;
      ushort temp = (ushort) (msg >> 16);
      writeData(portMessageHigh[reg], temp);
      temp = (ushort) (msg & 0xFFFF);
      writeData(portMessageLow[reg], temp);
      loadStatusRequest = FALSE;
   }
   writeAddress((uchar) (cmdSelectEvent | tdr));
   uchar cmd = regMessage[reg];
   cmd |= (cmdSingleMessage | tdr);
   writeAddress(cmd);
}

void TTdrControl::resetDsp(uchar tdr) {
   sendMessage(tdr, (ulong) msgResetDsp);
}

void TTdrControl::checkEventNumber(uchar tdr, ushort number) {
   int reg = 2;

   if ( loadCheckEvent ) {
      ulong msg = msgCheckEvent;
      ushort temp = (ushort) (msg >> 16);
      writeData(portMessageHigh[reg], temp);
   }
   writeData(portMessageLow[reg], number);
   loadCheckEvent = FALSE;
   uchar cmd = regMessage[reg];
   cmd |= (tdr == TDR_ALL ? cmdBrdCastMessage : (cmdSingleMessage | tdr));
   writeAddress(cmd);
}

void TTdrControl::setDAC(uchar tdr, ushort data) {
   sendMessage(tdr, (ulong) (msgSetDAC | data));
}

void TTdrControl::readRam(uchar *data, ushort len, ushort addr) {
   writeData(portEppAddress, addr);
   readData(portRamRegister, data, len);
}

void TTdrControl::selectSource(uchar tdr) {
   uchar cmd = (cmdSelectEvent | tdr);
   writeAddress(cmd);
}

void TTdrControl::sendCmd(uchar cmd) {
   writeAddress(cmd);
}


/*
ushort TTdrControl::dspStatus(uchar tdr, uchar *r) {
   writeAddress((uchar) (cmdSelectEvent | tdr));

   writeData(portSlinkAddress, (ushort) 0);
   writeData(portEppAddress, (ushort) 0);

   sendMessage(tdr, (ulong) msgDspStatus);

   // Wait with timeout
   clock_t end_time = clock() + 18;
   while ( !(getCSR1() & 2) ) {
      if ( clock() > end_time ) return FALSE;
   }

   ushort len = 0x2000;
   readData(portRamRegister, r, len);

   return len;
}
*/