| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| app|adc_data|\gen:3:U1|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:3:U1|U1 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:3:U1 |
5 |
0 |
1 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:2:U1|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:2:U1|U1 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:2:U1 |
5 |
0 |
1 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:1:U1|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:1:U1|U1 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:1:U1 |
5 |
0 |
1 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:0:U1|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:0:U1|U1 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data|\gen:0:U1 |
5 |
0 |
1 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|adc_data |
8 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:3:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:3:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:2:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:2:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:1:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:1:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:0:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a|\gen:0:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_a |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:3:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:3:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:2:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:2:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:1:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:1:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:0:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck|\gen:0:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_plllck |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_rsrload|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_rsrload|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_rsrload |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:3:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:3:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:2:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:2:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:1:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:1:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:0:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout|\gen:0:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_srout |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srclk|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srclk|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srclk |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srin|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srin|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_srin |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:3:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:3:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:2:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:2:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:1:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:1:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:0:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout|\gen:0:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_wsrout |
6 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_denable|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_denable|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_denable |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sdi|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sdi|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sdi |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sck|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sck|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_sck |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_eeprom_cs|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_eeprom_cs|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_eeprom_cs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_cs|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_cs|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_dac_cs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:3:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:3:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:2:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:2:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:1:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:1:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:0:U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a|\gen:0:U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_ts_cs_a |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sck|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sck|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sck |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sdi|U1|ALTDDIO_OUT_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sdi|U1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|obuf_drs_sdi |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_sdo|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_sdo|U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| app|ibuf_drs_sdo |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| app |
895 |
187 |
696 |
187 |
962 |
187 |
187 |
187 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_start|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_start|U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_start |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flagc|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flagc|U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flagc |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flaga|U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flaga|U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_flaga |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:31:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:31:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:30:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:30:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:29:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:29:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:28:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:28:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:27:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:27:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:26:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:26:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:25:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:25:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:24:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:24:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:23:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:23:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:22:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:22:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:21:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:21:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:20:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:20:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:19:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:19:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:18:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:18:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:17:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:17:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:16:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:16:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:15:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:15:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:14:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:14:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:13:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:13:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:12:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:12:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:11:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:11:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:10:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:10:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:9:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:9:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:8:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:8:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:7:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:7:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:6:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:6:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:5:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:5:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:4:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:4:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:3:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:3:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:2:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:2:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:1:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:1:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:0:U1|ALTDDIO_IN_component|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i|\gen:0:U1 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc|ibuf_data_i |
34 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_usb3_racc |
551 |
0 |
2 |
0 |
655 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:7:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:7:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:6:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:6:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:5:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:5:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:4:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:4:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:3:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:3:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:2:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:2:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:1:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:1:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:0:U0|altsyncram_component|auto_generated |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| \gen_dpram_readout:0:U0 |
92 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|mux5 |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|mux4 |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|decode3 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated|decode2 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom|altsyncram_component|auto_generated |
96 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_drs_dpram_eeprom |
96 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led7 |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| led6 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led5 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led4 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| spiadc0 |
3 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| C_clk132_pll|t1_pll_132_inst |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| C_clk132_pll |
2 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |