Computing engineer
for the ATLAS TDAQ HL-LHC upgrade

The Department of Nuclear and Particle Physics (DPNC) of the University of Geneva invites applications for an engineer to work on heterogeneous computing developments for the ATLAS Trigger and Data Acquisition (TDAQ) HL-LHC upgrade.

The DPNC has made significant contributions to the construction and the operation of the ATLAS experiment. It is currently involved in the HL-LHC upgrades of the ATLAS tracker and TDAQ systems.

Job Description

The successful candidate will join the TDAQ upgrade activity, and more specifically the Event Filter project. The Event Filter design is based on a heterogeneous computing system that consists of CPU cores and possibly accelerators. It will be processing data in real-time at a rate of 1 MHz. Fast algorithms will be selecting 1% of these events for storage.

The engineer will contribute to the development of a heterogeneous computing architecture accelerated using FPGAs. (S)he will participate in system design, performance evaluation and integration. The work will include the realisation of a demonstrator set-up that uses a Xilinx Versal card as an accelerator. A specific sequence of algorithms (jet finding) will be used as a test case. This sequence will be composed of both conventional and machine-learning-based algorithms, developed following real-time constraints.

The projects will be in close collaboration with physicists and engineers from the University of Geneva and other institutes from all over the world participating to the ATLAS TDAQ HL-LHC upgrade.

Required qualifications and skills

  • Master’s degree or PhD in Computer Science, Engineering or other related field
  • Experience in computer architectures
  • Strong software-development experience
  • Familiarity with HLS or other FPGA-based prototyping and emulation tools
  • English fluency
  • Excellent oral and written communication skills
  • The ability to work in a collaborative environment with researchers from all over the world
  • Initiative and autonomy

    The following are a plus:

  • Knowledge of data center FPGA acceleration technologies
  • Knowledge of hardware description languages, such as VHDL or Verilog
  • Knowledge in version management and configuration tools (e.g. github)
  • Test coverage control (unit / integration)
  • Experience with machine learning
  • Experience with optimisation of hardware for machine learning and other algorithms

    Employment conditions

    The position is to be filled as soon as a suitable candidate is selected. The successful candidate will be expected to start in autumn 2022. (S)he will be offered an initial 2-year contract, with an extension possible depending on funding availability.

    Location: University of Geneva, Section de Physique, DPNC -- 24, quai Ernest Ansermet, CH-1205, Geneva.

    How to apply

    Please follow the link at the bottom of this page. The review of the applications will start immediately and the position will be filled when a suitable candidate is found. For full consideration, please apply by 31 July 2022.

    UniGe is an equal opportunity employer. Diversity is central to our success.

    For additional information please contact Prof. Anna Sfyrla (

    Page last updated on 21 June 2022.